1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, to a thin film transistor (TFT).
2. Description of Related Art
FIG. 1 shows a schematic cross-sectional view of a conventional thin film transistor. As shown in FIG. 1, a thin film transistor 100 comprises a substrate 110, an insulating layer 120, an island polysilicon 140, a carrier tunneling layer 152, a carrier trapping layer 154, a carrier blocking layer 156 and a gate 160. The insulating layer 120, the island polysilicon layer 140, the carrier tunneling layer 152, the carrier trapping layer 154, the carrier blocking layer 156 and the gate 160 are sequentially disposed over the substrate 110.
In the island polysilicon 140, two N-type doped regions are used as a source 140a and a drain 140b and a region between the source 140a and the drain 140b is used as a channel 140c. Moreover, each of the source 140a, the drain 140b and the channel 140c has a peak structure P and the peak structures P are formed by the sequential lateral solidification (SLS) laser crystallization with complex process procedures.
As for the nonvolatile memory constructed by the thin film transistors 100, these peak structures P can be used to enhance the strength of the electric field so as to improve the efficiency of the program operation and erase operation. However, by using the sequential lateral solidification laser crystallization, there are problems such as uncontrollable height of the peak structure P and inaccurate alignment between the peak structure P and other film layers. Therefore, the uniformity of the electrical performances of the thin film transistors 100 is poor and the efficiency of the program operation and the erase operation of the nonvolatile memory is decreased so as to decrease the yield of the thin film transistor 100.